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Seokin Hong, Ph.D.


Email: seokin@kaist.ac.kr

Research Interests
  • Fault tolerant computer architecture
  • Energy efficient computer architecture
  • Memory system (DRAM, PRAM, STT-RAM)



Awards
  • Best Paper Award, Design Automation and Test in Europe Conference (DATE’13), Grenoble, France, 2013
  • Best Paper Award, 29th IEEE International Conference on Computer Design (ICCD'10), Amsterdam, the Netherlands, 2010


Publications
  • Seokin Hong and Soontae Kim. A Low-cost Mechanism Exploiting Narrow-width Values for Tolerating Hard Faults in ALUTo appear in IEEE Transactions on Computers (TC).
  • Tayyeb Mahmood, Seokin Hong, and Soontae Kim. Ensuring cache reliability and energy scaling at near-threshold voltage with MachoTo appear in IEEE Transactions on Computers (TC).
  • Seokin Hong, Jongmin Lee, and Soontae Kim, Ternary Cache: Three-valued MLC STT-RAM Caches, IEEE International Conference on Computer Design (ICCD'14), Seoul, Korea, Oct. 19-22 2014. (63 papers accepted out of 202 submissions, 31% acceptance rate, Best Paper Nominee)
  • Seokin Hong and Soontae Kim. AVICA: An Access-time Variation Insensitive L1 Cache Architecture. Design Automation and Test in Europe Conference (DATE’13), Grenoble, France, March 18~22 2013. (206 papers accepted out of 829 submissions, 24.8% acceptance rate, Best Paper Award)
  • Yebin Lee, Soontae Kim, Seokin Hong, and Jongmin Lee. Skinflint DRAM System: Minimizing DRAM Chip Writes for Low  Power. The 19th IEEE International Symposium on High Performance Computer Architecture (HPCA'13), Feb. 23-27, 2013, Shenzhen, China. (51 papers accepted out of 249 submissions, 20% acceptance rate)
  • Tayyeb Mahmood,  Soontae Kim, and Seokin Hong. Macho: A Failure Model-oriented Adaptive Cache Architecture to enable Near-Threshold Voltage Scaling. The 19th IEEE International Symposium on High Performance Computer Architecture (HPCA'13), Feb. 23-27, 2013, Shenzhen, China. (51 papers accepted out of 249 submissions, 20% acceptance rate)
  • Soontae Kim, Jesung kim, Jongmin Lee, and Seokin Hong, Residue Cache: A Low-Energy Low-Area L2 Cache Architecture via Compression and Partial Hits, The 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO’11), Dec. 3~7, Brazil. (44 papers accepted out of 209 submissions, 21% acceptance rate)
  • Jongmin Lee, Seokin Hong, Soontae Kim. TLB Index-based Tagging for Cache Energy Reduction, The International Symposium on Low Power Electronics and Design (ISLPED’11), Fukuoka, Japan, Aug. 1~3, 2011. (45 papers accepted out of 201 submissions, 22.4% acceptance rates)
  • Seokin Hong and Soontae Kim, Lizard: Energy-efficient Hard Fault Detection, Diagnosis and Isolation in the ALU. 29th IEEE International Conference on Computer Design (ICCD'10), Amsterdam, the Netherlands, Oct. 3-6 2010. (79 papers accepted out of 267 submissions, 29% acceptance rateBest Paper Award)
  • Seokin Hong and Soontae Kim, TEPS: Transient error protection utilizing sub-word parallelism. IEEE International Symposium on VLSI (ISVLSI'09), Tampa, FL, USA, May 13-15 2009. (34 papers accepted out of 138 submissions, 24.6% acceptance rate)


Patents 
  • Seokin Hong and Soontae Kim, "Cost-efficient Hard Fault Tolerant ALU (영구적 오류에 강인한 저비용 n 비트 산술논리연산기)", KR Patent No. 1011817950000, 5 September 2012.


Experiences
  • Electronics and Telecommunications Research Institute (ETRI), Korea
    • Intern in system software group, Feb. 2009 ~ Aug. 2009 
  • Samsung Software Membership (SSM), Korea
    • SMP operating system, Apr. 2008 ~ Jun. 2008
    • COBOT project (Adhoc network based Cooperative Robots), Jul. 2007 ~ Feb. 2008
  •  Sungkyunkwan Institute Of Robot (SIOR), Korea
    • Vision based object tracking robot, Jun. 2007 ~ Dec. 2007
    • Motion recognition system using MHI, Jun. 2006 ~ Dec. 2006
    • Embedded image processing board, Aug. 2005 ~ Dec. 2005