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Jongmin Lee, Ph.D.

Email: square55@kaist.ac.kr

Research Interests
  • Embedded System Design
  • Computer Architecture
  • Power Efficient Architecture Design

Publications

  • Jongmin Lee and Soontae Kim. Filter Data Cache: An Energy-Efficient Small L0 Data Cache Architecture Driven by Miss Cost Reduction. To appear in IEEE Transactions on Computers.
  • Seokin Hong, Jongmin Lee, and Soontae Kim, Ternary Cache: Three-valued MLC STT-RAM Caches, IEEE International Conference on Computer Design (ICCD'14), Seoul, Korea, Oct. 19-22 2014.
  • Yebin Lee, Soontae Kim, Seokin Hong, and Jongmin Lee. Skinflint DRAM System: Minimizing DRAM Chip Writes for Low  Power. IEEE International Symposium on High Performance Computer Architecture (HPCA'13), Feb. 23-27, Shenzhen, China, 2013.
  • Jongmin Lee and Soontae Kim, Adopting TLB Index-based Tagging to Data Caches for Tag Energy Reduction, ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED’12), California, USA, Jul. 30 ~ Aug. 1, 2012.
  • Soontae Kim, Jesung kim, Jongmin Lee, and Seokin Hong, Residue Cache: A Low-Energy Low-Area L2 Cache Architecture via Compression and Partial Hits, In Proc. of IEEE/ACM International Symposium on Microarchitecture (Micro’11), Dec. 3~7, 2011.
  • Jongmin Lee, Seokin Hong, Soontae Kim. TLB Index-based Tagging for Cache Energy Reduction (long paper), ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED’11), Fukuoka, Japan, Aug. 1~3, 2011.
  • Soontae Kim and Jongmin Lee. Write buffer-oriented energy reduction in the data cache of two-level caches for the embedded systems. ACM Great Lakes Symposium on VLSI (GLSVLSI’10), Providence, USA, May 16~18, 2010.
  • Jongmin Lee, Soontae Kim, Energy-delay efficient 2-level data cache architecture for embedded systems. In Proc. of  ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED’09), San Francisco, CA, USA, Aug. 2009.

Domestic Publications
  • Jongmin Lee and Soontae Kim. Energy-delay efficient 2-level data cache architecture for embedded system. Journal of KIISE, Oct. 2010.
  • Jongmin Lee, Soontae Kim, et. al, Low-Power 2-level Cache Architectures for Embedded system,  KIPS Fall Conference, 2008.
Experiences
  • Electronics and Telecommunications Research Institute (ETRI), Korea
    • Intern in embedded SW flatform group, Feb. 2009.