Members‎ > ‎

Jesung Kim, Ph.D. Student

Email: jesung.kim@kaist.ac.kr

Research Interests
  • Reliable Embedded System Design
  • Reliable Cache Architecture Design

Publications
  • Myeongjae Jang, Jinkwon Kim, Jesung Kim, and Soontae Kim, "ENCORE Compression: Exploiting Narrow-width Values for Quantized Deep Neural Networks," accepted for Design, Automation, and Test in Europe Conference (DATE'22).
  • Jesung kim, Jongmin Lee, and Soontae Kim, "TLB Index-based Tagging for Reducing Data Cache and TLB Energy Consumption," IEEE Transactions on Computers (TC), Vol. 66, No. 7, pp. 1200-1211, Jul. 2017.
  • Jeongkyu Hong*, Jesung Kim*, and Soontae Kim, "Exploiting Same Tag Bits to Improve the Reliability of the Cache Memories," IEEE Transactions on VLSI Systems (TVLSI), Vol. 23, No. 2, pp. 254-265, Feb. 2015. (*equal contribution).
  • Soontae Kim, Jesung kim, Jongmin Lee, and Seokin Hong, "Residue Cache: A Low-Energy Low-Area L2 Cache Architecture via Compression and Partial Hits,"  IEEE/ACM International Symposium on Microarchitecture (MICRO’11), Dec. 3~7, 2011, Brazil (44 papers accepted out of 209 submissions, 21% acceptance rate).
  • Jesung kim, Soontae Kim, and Yebin Lee, "SimTag: Exploiting Tag Bits Similarity to Improve the Reliability of the Data Caches,"  Design Automation and Test in Europe Conference (DATE’10), Dresden, Germany, March 8~12 2010. (30% acceptance rate).

Experiences


Comments